The present invention relates generally to semiconductor devices and more particularly to the architectural layout of semiconductor memory devices.
Various types of semiconductor memory devices for storing binary information have been known and commercially available for many years. A very popular category of semiconductor memory is dynamic random access memory (DRAM), in which binary data (xe2x80x9c1""sxe2x80x9d and xe2x80x9c0xe2x80x2sxe2x80x9d) is represented by the presence or absence of electrical charges on storage capacitors. Typically, a DRAM comprises a plurality of memory cells each consisting of a storage capacitor and at least one access transistor for controlling the reading or writing of the cell, i.e., the application or removal of charge or the detection of the presence or absence of charge on the capacitor. The memory cells are normally arranged in a two-dimensional array of rows and columns of memory cells, with the columns extending in a direction substantially perpendicular to the rows.
In a typical DRAM, accessing one (or more) cells in the array involves the application of a row address and a column address to the device""s external address input terminals; such addresses usually take the form of multiple-bit binary numbers represented by electrical logic signals having one of two possible voltage levels. Addressing circuitry associated with the memory array decodes the row and column addresses to generate the access signals appropriate to access the designated cell(s). The access signals are routed to the access transistor(s) for the designated cell(s), and the read or write operation is performed.
During a read operation, an accessed cell""s storage transistor is coupled to a sense amplifier which senses and amplifies the presence or absence of a voltage stored on the capacitor. The sense amplifier output, in turn, is applied to a hierarchy of data input/output (I/O) lines, sometimes called a xe2x80x9cdata path,xe2x80x9d such that the voltage representative of a binary xe2x80x9c1xe2x80x9d or a binary xe2x80x9c0xe2x80x9d is propagated to the memory device""s external I/O terminals. (It is assumed for the purposes of the present disclosure that those of ordinary skill in the art are familiar conceptually with the representation of binary xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d values using electrical signals having one of two logical levels, for example, a zero voltage representing a binary xe2x80x9c0xe2x80x9d and a voltage of 3.3V representing a binary xe2x80x9c1,xe2x80x9d or vice versa.) During a write operation, the opposite occurs. The value (voltage) to be written to a particular cell is applied to the external I/O terminal and conveyed on the internal data path to the cell identified by an externally applied row and column address pair. When the designated cell is accessed, its access transistor couples the cell""s storage capacitor to the data line, such that if a non-zero voltage is present on the data line, that voltage is stored on the capacitor.
Those of ordinary skill in the art will appreciate that the foregoing description in some respects simplifies the underlying mechanisms and procedures involved in the operation of a semiconductor memory. The operation of each sense amplifier in sensing the logic level voltage stored on a given memory cell storage capacitor, for example, is itself a complex process involving the precise generation and timing of a number of internal control signals, as well as the application of carefully regulated power signals. In addition to the necessity of providing conductive lines to communicate these many signals to the appropriate locations upon the silicon substrate, additional areas of the device must be occupied by the control circuitry required to accomplish the read and write operations of a memory device. Functional elements of a memory device, peripheral to and/or interspersed with the memory cells themselves, include sense amplifier circuitry, power supply and regulation circuitry, row and column address decoding circuitry, and the often intricate data path for communicating logic voltages to and from the memory storage cells. The particular arrangement and distribution of all such functional elements is commonly referred to as the architecture of a memory device.
Those of ordinary skill in the art will be familiar with a number of countervailing considerations implicated in the architectural layout and fabrication of semiconductor memory devices. Often foremost among these considerations is the objective of maximizing device density and capacity, i.e., providing the greatest number of individual memory cells in the smallest amount of substrate area. Using currently state-of-the-art design and fabrication techniques, it is possible to provide memory devices capable of storing 256 megabits of data or more on a single substrate. The quest to achieve ever-greater storage capacities and storage densities is ongoing within the semiconductor industry.
Maximizing the operational speed of semiconductor memories is another ongoing design objective. Operational speed refers to the rate at which data can be written into and read out from the memory device. In state-of-the-art memory devices, hundreds or thousands of read and/or write operations can be performed in one second. Like device density, attempts to maximize operating speed are ongoing in the semiconductor industry.
Those of ordinary skill in the art will appreciate that some of the techniques used to achieve one particular design objective can have adverse consequences with respect to other objectives. For example, one obvious approach to maximizing memory capacity and density is to minimize the size of the various semiconductor structuresxe2x80x94transistors, capacitors and the likexe2x80x94making up the memory. However, decreasing structure sizes can have an adverse impact upon the memory""s speed; reducing the size of memory cell storage capacitors means that less charge can be stored on each capacitor, and with less charge to sense, the sense amplifiers"" response times are likely to be increased.
Likewise, while it may be desirable from the standpoint of device density to form semiconductor structures in a physically dense and close relationship on the substrate, such a design philosophy can lead to such problems as interference and/or cross-coupling of electrical signals in the memory, thereby having an adverse impact on other operational characteristics, such as reliability or speed. It is the challenge facing semiconductor device designers to reconcile such countervailing considerations and reach acceptable compromises with respect to the various design objectives and performance criteria. Of course, overriding all such considerations are numerous practical limitations, such as limitations on the physical size of semiconductor structures that can be formed on a silicon substrate using existing fabrication technology.
In order to arrive at a design which achieves an acceptable a balance between the many countervailing considerations associated with semiconductor memory architectures, memory designers must take into account the overall architectural layout of the device in order to recognize the potential adverse consequences of measures taken to improve one device characteristic upon all other relevant characteristics.
In view of the foregoing and other considerations, the present invention relates to an improved architecture for a semiconductor memory device. In accordance with one embodiment of the invention, a semiconductor memory device is organized in such a way that undesirable interference and cross-coupling between various signals generated during operation of the device is minimized. By minimizing such undesirable effects in particular ways, other device characteristics, such as the size of various circuit elements, can advantageously also be optimized.
In one embodiment of the invention, a semiconductor memory device comprising an array of rows and columns of memory cells is organized logically and physically into a plurality of sub-arrays. Within each sub-array, the memory cells are organized logically and physically into a plurality of dependent, interleaved banks of memory cells. The banks of memory cells, in turn, each comprise a plurality of memory cores comprising a plurality of memory cells. The memory cores are arranged in such a way as to define a plurality of substantially elongate, orthogonal xe2x80x9cstripesxe2x80x9d therebetween. Row decoder circuitry for selecting a specified row of memory cells is disposed along the stripes extending in a first direction. Sense amplifier circuitry for detecting the state of selected memory cells is disposed along stripes extending in a second direction, substantially perpendicular to the first direction.
In accordance with one aspect of the invention, column decode circuitry is disposed along one edge of each memory sub-array such that column select signals propagate along a direction substantially parallel to the stripes of row decoder circuitry. In accordance with another aspect of the invention, array control circuitry for generating various control signals activated throughout the course of a memory access (read and/or write) cycle is disposed proximal the column decode circuitry, such that the various control signals propagate along a direction substantially parallel to the column select signals.
By ensuring that the control signals, power signals, and column select signals all propagate substantially in parallel, cross-talk and interference among the various internal signals is minimized.
In accordance with another aspect of the invention, sense amplifier output signals are routed to input/output (I/O) circuitry disposed alongside each sub-array. Due to the interleaved banking arrangement of the memory array, the number of banks that the I/O path crosses as the sensed data is propagated to the I/O circuitry is minimized. The interleaved banking arrangement further minimizes the number of banks which share any given power strap.